AURIX TC3xx: 32-Bit Multicore Microcontroller Family (Aurix-2G Second Generation)

• Infineon AURIX 2G Architecture
  • Multicore architectural blocks
  • Interconnectivity
  • Consequences for software architectures
• CPU Subsystem
  • Multicore instruction set extensions
  • Registers files and context switching
  • Memory protection unit (software monitoring)
• Internal Connectivity
  • Crossbar and peripheral bus
  • CPU clustering
  • Performance aspects for software
• Memory
  • Memory map
  • Configuration options
  • Cache and software handling
  • Types
  • Hierarchy
  • Test
• Infineon Low-Level Drivers: Overview
  • Configuration structures
  • Application programming interface
  • Library distribution
  • Frameworks and demos
• Ports
• Exceptions and Handling
  • Traps (hardware and software)
  • Interrupts (hardware and software)
  • Vector tables
  • Broadcast software interrupts (core synchronization)
  • External interrupts
• Direct Memory Access Controller DMA
  • Move engines
  • Triggering (hardware and software)
  • Advanced features (software relaxation)
• Timer
  • System timer (STM)
  • General purpose timer 12 (GPT12)
  • Capture compare unit (CCU)
  • Watchdog timer (WDT)
  • Temporal protection timer (TPS, exception timer)
  • Generic timer module (GTM) - overview
• Safety and Security
  • Safety measures
  • Safety management unit (SMU)
  • Protection mechanisms
  • IO monitoring
  • Hardware security module (HSM) - implementation overview
• Multicore Aspects
  • Startup and boot
  • Low power options
  • Communication and synchronization
  • Intrinsics usage in C/C++
  • Tool aspects (compiler, linker)
  • Debugging (AMP, SMP)
• System Control
  • Reset: sources, types and consequences
  • Boot: software configuration and modes
  • Clocking
  • Emergency stop requests
• Power Management System (PMS)
  • Supply generation options
  • Embedded voltage regulators
  • Standby and wakeup
  • Die temperature sensor
• Synchronous and Asynchronous Standard Peripherals
  • Micro second channel (MSC)
  • Serial peripheral interface (QSPI)
  • Inter IC interface (I2C)
  • UART (ASCLIN)
• Sensor Interfaces
  • SENT
  • PSI5
  • PSI5-S
• Analog To Digital Converter
  • EVADC
  • EDSADC
  • Enhanced features offloading software
• Automotive Interfaces: Overview
  • LIN
  • CAN
  • FlexRay
• High Speed Serial Link Interface (HSSL)
• Ethernet: Overview/Demo
• Debug
  • Interfaces
  • Tracing
  • Multicore aspects
• Exercises
  • Numerous exercises will be conducted on an Infineon AURIX board, covering the following aspects: use of low-level drivers, protection mechanisms, interrupt controller, DMA controller, system timer, port, multicore aspects, monitoring, performance measurement etc.
• IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the Aurix-2G training course.
• Please note that the Aurix-2G training does not explicitly cover ADAS specific blocks. If required, please contact our service office prior to the training, phone +49 (0)89 450617-71.

Lernziele

• You know the architecture, basic on-chip peripherals and the features (especially related to multicore and safety extensions) of the AURIX device family.
• You get to apply low-level drivers for this hardware, adapt examples as required and test them with a debugger.
• Numerous exercises make this training a practice-oriented software workshop.
• YOUR BENEFIT:
• Efficient and compact jump-start into the overall topic
• Practical tips on multicore and safety
• Exercises on USB stick or as download.

Zielgruppe

• Hardware and software architects, hardware and software developers, test engineers // IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the Aurix-2G training course.

Voraussetzungen

• ANSI-C knowledge; experience in microcontroller/microprocessor system programming and architecture